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        <h3 id="1-画框图"><a href="#1-画框图" class="headerlink" title="1.画框图"></a>1.画框图</h3><p>​        先设计LED的框图，模块有两个信号，一个是输入信号，一个是输出信号。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191421776.png" style="zoom:50%;">

<h3 id="2-画波形图"><a href="#2-画波形图" class="headerlink" title="2.画波形图"></a>2.画波形图</h3><p>​        具体模块的功能使用波形图来实现：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191456794.bmp" style="zoom:87%;">

<p>输出波形和输入波形是一样的。</p>
<h3 id="3-代码编写"><a href="#3-代码编写" class="headerlink" title="3.代码编写"></a>3.代码编写</h3><p>​        按博文《Vivado新建ZYNQ工程》中建立好工程后，在工程管理栏点击 Add Sources 添加我们需要编写设计的led灯代码文件：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191600255.png" style="zoom:67%;">

<p>​        弹出的界面勾选 Addorcreatedesignsources，表示添加或者新建一个设计文档，然后点击 next</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191602852.png" style="zoom:67%;">

<p>​        然后点击 Create File ,弹出的子对话框中，File Type 默认是 verilog，File Name 填入 verilog 文件名，我们这里填入的是 led。然后点击 OK</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191606344.png" style="zoom:67%;">

<p>​        点击 Finish 完成文档创建。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191611681.png" style="zoom:47%;">

<p>​        点击Finish 之后，弹出对应文档的模块名称。这里我们默认led，然后点击OK。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191614263.png" style="zoom:60%;">

<p>​        我们可以看到，led模块和文档已经在设计文件层次窗口中:</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191615526.png" style="zoom:67%;">

<p>​        我们双击打开 led, 然后对其进行编辑，添加如下代码</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191627051.png" style="zoom:67%;">

<p><strong>语法补充：assign语句</strong></p>
<p>​        被assign语句赋值的信号通常我们要定义成wire类型。</p>
<h3 id="4-综合"><a href="#4-综合" class="headerlink" title="4.综合"></a>4.综合</h3><p>​        开始综合，点击工程管理栏的 Run Synthesis：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191633315.png" style="zoom:60%;">

<p>​        然后弹出的 Launch Runs 对话框根据电脑配置选择 Jobs 数量（代表综合消耗的进线程，VIVADO 目前已验证过支持 12 线程，  综合过程很耗 CPU性能，所以如果想要综合过程中流畅使用电脑，可以少选两个线程。选完线程数量，点击OK 进行综合。（综合过程很慢，请耐心等待）</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191636607.png" style="zoom:67%;">

<p>​        综合状态可以在右上角看到已经开始运行。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191637365.png" style="zoom:67%;">

<p>​        完成综合后，<strong>弹出的综合完成对话框中我们点击 Cancel 取消。不要进行 Implementation</strong>。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191639006.png" style="zoom:50%;">

<h3 id="5-管脚绑定"><a href="#5-管脚绑定" class="headerlink" title="5.管脚绑定"></a>5.管脚绑定</h3><p>​        由于我们还没有进行管脚绑定，所以我们需要先绑定管脚再进行 Implementation 实现，最后<br>布局布线最后生成 BIT 文件。我们接下来进行绑定管脚。我们点击工程管理栏的 RTL ANALYSIS<br>下面的&gt;open Elaborated Design：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191642974.png" style="zoom:67%;">

<p>弹出的对话框我们选择 OK。</p>
<p>​        然后右上角，软件运行状态下面的视图选择。我们默认是 Default Layout，但是我们要进行IO 绑定，我们选择 I/O Planning。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191644557.png" style="zoom:67%;">

<p>选择 I/O Planning 之后出现如下视图，在下面窗口部分，I/O Ports 即可进行 IO 管脚绑定。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191649748.png" style="zoom:60%;">

<p>​        根据原理图绑定的管脚如下所示：（电平标准都选择 LVCMOS33）</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191656397.png" style="zoom:80%;">

<p>​        按下 ctrl+s 保存，弹出的保存对话框，填入管脚约束文件名。我们这里取为 led</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191658163.png" style="zoom:67%;">

<h3 id="6-布局布线生成bit文件"><a href="#6-布局布线生成bit文件" class="headerlink" title="6.布局布线生成bit文件"></a>6.布局布线生成bit文件</h3><p>​        我们点击工程管理栏的 PROGRAM AND DEBUG 下面的 Generate Bitestream 生成 BIT文件。（也可以先点击 IMPLEMENTATION 下面的 Run implementation 先进行实现，实现包括布局布线，<strong>这里直接生成 bit 文件包含了实现操作</strong>）。弹出的对话框为综合信息过期。这里默认点击 OK（由于软件综合后才能有模块的顶层引脚信息，才能进行绑定管脚。我们绑定管脚之后，软件认为工程信息发生了变更所以需要再次综合）。</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191703889.png" style="zoom:60%;">

<p>​        接着还会弹出综合线程数量对话框。我们也选择默认，然后点击OK。然后软件开始了生成比特流的一系列工作。流程是：综合-&gt;实现（布局布线）-&gt;生成bit 文件。我们等待软件运行这些操作结束，结束后弹出如下对话框，这里我们选择打开硬件管理器 Open Hardware Mnager:</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191705970.png" style="zoom:67%;">

<h3 id="7-烧录bit文件"><a href="#7-烧录bit文件" class="headerlink" title="7.烧录bit文件"></a>7.烧录bit文件</h3><p>​        弹出的硬件管理界面，这个时候可以插上我们的ZYNQ开发板的下载器USB接口（TYPE-C的DEBUG口）进行调试。如果开发板黄色LED亮起，说明开发板已经上电，可以连接。点击上方的Open Target:</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191707429.png" style="zoom:87%;">

<p>弹出的下拉界面选择点击 Auto target，自动连接目标开发板。点击之后待连接完成。</p>
<p>​        连接完成之后，可以看到 Hardware 窗口出现了两个设备，一个是arm的dap，一个是xc7z010 芯片。<strong>上方我们点击Program Device进行烧写配置</strong>（断电就丢失。需要下载到 FLASH的教程我们在后面介绍步骤）</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191714058.png" style="zoom:67%;">

<p>弹出的烧写对话框，默认都不改动，其中Bitstream file表示选择的bit文件，也就是上面我们生成的bit文件。点击 program：</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/202302191715381.png" style="zoom:67%;">

<p>烧写完成，我们按下key2，led1灭；松开key2，led1亮。本节教程结束。</p>

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